參數(shù)資料
型號(hào)： 94201DF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, ROHS COMPLIANT, SSOP-56
文件頁(yè)數(shù)： 16/21頁(yè)
文件大?。?/td> 222K
代理商： 94201DF
4
ICS94201
0428B - 11/28/05
Notes:
1.
The ICS clock generator is a slave/receiver, I
2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to read back is defined
by writing to byte 6.
2.
When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8-bit bytes.
6.
To simplify the clock generator I
2C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Register Name
Byte
Description
Pw d Default
Func tionality & Frequenc y Select
Register
0
Output frequency, hardware / I
2C frequency
select, s pread spectrum & output enable
control register.
See individua l byte
des cription
Output Control Registers
1-5
Active / inactive output control registers.
See individua l byte
des cription
Byte Count Read Back Register
6
W riting to this register will c onfigure by te
count and how many byte will be read back.
Do not write 00H to this byte.
06H
Latc hed Inputs Read Back
Register
7
The inverse of the latched inputs level could
be read back from this regis ter.
See individua l byte
des cription
W atchdog Control Regis ters
8 Bit[6:0]
W atchdog enable, watchdog status and
program mable 'safe' frequenc y' can be
configured in this register.
000,0000
VCO Control S election B it
8 Bit[7]
This bit selects whether the output
frequenc y is controled by hardware/by te 0
configurations or byte 14&15 programm ing.
0
W atchdog Tim er Count Register
9
W riting to this register will c onfigure the
number of seconds for the watchdog timer
to reset.
FFH
ICS Reserved Register
10
This is an unused register. W riting to this
register will not affect device functionality.
00H
Device ID, Vendor ID & Revision ID
Registers
11-12
Byte 11 bit[3:0] is ICS vendor id - 0001.
Other bits in these 2 registers designate
device revision ID of this part.
See individua l byte
des cription
ICS Reserved Register
13
Don't write into this register, writing 1's will
cause m alfunction.
00H
VCO Frequenc y Control Registers
14-15
These registers control the dividers ratio
into the phase detector and thus control the
VCO output frequency.
Depend on
ha rdware/byte 0
configuratio n
Spread Spectrum Control
Registers
16-17
These registers control the s pread
percentage amount.
Depend on
ha rdware/byte 0
configuratio n
Output Dividers Control Registers
18-20
Changing bits in these regis ters result in
frequenc y divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system malfunction.
Depend on
ha rdware/byte 0
configuratio n
Group Skews Control Registers
21-23
Increment or decrement the group skew
amount as compared to the initial skew.
See individua l byte
des cription
Output Rise/Fall Time S elect
Registers
24
These registers will control the group rise
and fall time.
See individua l byte
des cription
Brief I
2C registers description for ICS94201
Programmable System Frequency Generator
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