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參數(shù)資料
| 型號(hào)： | 935270253112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 65K |
| 代理商： | 935270253112 |
Philips Semiconductors
Product data
HSTL16918
9-bit to 18-bit HSTL-to-LVTTL memory address latch
2001 Jun 16
6
VOLTAGE WAVEFORMS
1.25 V
0.25 V
INPUT
tw
VREF
SW00770
Figure 1. Pulse duration
1.25 V
0.25 V
DATA INPUT
VREF
LE
tsu
th
1.25 V
0.25 V
SW00771
Figure 2. Setup and Hold times
VREF
1.5 V
1.25 V
0.25 V
VOH
VOL
tPHL
tPLH
INPUT
(Note 1)
OUTPUT
SW00772
Figure 3. Propagation delay times
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 1 ns, tf ≤ 1 ns.
2. The outputs are measured one at a time with one transition per
measurement.
3. tPHL and tPLH are the same as tpd.
LOAD CIRCUIT
CL = 80 PF
(see Note)
500
FROM OUTPUT
UNDER TEST
SW00773
NOTE: CL includes probe and jig capacitance.
Figure 4. Load circuit
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