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參數(shù)資料
| 型號： | 935270253112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 935270253112 |
Philips Semiconductors
Product data
HSTL16918
9-bit to 18-bit HSTL-to-LVTTL memory address latch
2001 Jun 16
3
PIN DESCRIPTION
PIN
SYMBOL
FUNCTION
4, 5, 7, 8, 16, 17,
18, 20, 21
D[1–9]
Inputs
2, 46, 43, 40, 37,
34, 31, 28, 24
1Q[1–9]
Outputs
1, 45, 42, 39, 36,
33, 30, 27, 23
2Q[1–9]
Outputs
10
1LE
Latch enable
14
2LE
Latch enable
12
VREF
Reference voltage
6, 19, 25, 26, 32,
41, 47, 48
VCC
Supply voltage
3, 9, 11, 13, 15,
22, 29, 35, 38, 44
GND
Ground
LOGIC DIAGRAM (positive logic)
2
10
1LE
4
D1
1Q1
1D
C1
1
14
2LE
2Q1
1D
C1
TO EIGHT OTHER CHANNELS
SW00769
VREF 12
FUNCTION TABLE
INPUTS
OUTPUT
LE
D
Q
L
H
L
H
X
Q0 1
NOTE:
1. Output level before the indicated steady-state input conditions
were established.
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