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參數(shù)資料
| 型號： | 935270056529 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 680K |
| 代理商： | 935270056529 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
12 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
It is assumed that software ow control and hardware ow control will never be
enabled simultaneously. Figure 7 shows an example of software ow control.
6.3.3
Software ow control example
Assumptions: UART1 is transmitting a large text le to UART2. Both UARTs are
using software ow control with single character Xoff (0F) and Xon (0D) tokens. Both
have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to
32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.
UART 1 begins transmission and sends 52 characters, at which point UART2 will
generate an interrupt to its processor to service the RCV FIFO, but assume the
interrupt latency is fairly long. UART1 will continue sending characters until a total of
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1,
informing UART1 to halt transmission. UART1 will likely send the 61st character while
UART2 is sending the Xoff character. Now UART2 is serviced and the processor
reads enough data out of the RX FIFO that the level drops to 32. UART2 will now
send a 0D to UART1, informing UART1 to resume transmission.
6.4 Reset
Table 4 summarizes the state of register after reset.
Fig 7.
Software ow control example.
TRANSMIT FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon-1 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-2 WORD
RECEIVE FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon-1 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-2 WORD
UART2
UART1
002aaa229
DATA
Xoff–Xon–Xoff
COMPARE
PROGRAMMED
Xon-Xoff
CHARACTERS
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