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參數(shù)資料
| 型號： | 935270056529 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, MS-018, SOT-188-2, LCC-68 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大?。?/td> | 680K |
| 代理商： | 935270056529 |
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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Product data
Rev. 02 — 14 March 2003
30 of 49
9397 750 11192
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud
clock in the baud rate generator. DLH stores the most signicant part of the divisor.
DLL stores the least signicant part of the divisor.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,
before IER[4] is set.
7.12 Transmission control register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start
transmission during hardware/software ow control. Table 20 shows transmission
control register bit settings.
TCR trigger levels are available from 0-60 bytes with a granularity of four.
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The
programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no
built-in hardware check to make sure this condition is met. Also, the TCR must be
programmed with this condition before Auto-RTS or software ow control is enabled
to avoid spurious operation of the device.
7.13 Trigger level register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed
with a granularity of 4. Table 21 shows trigger level register bit settings.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60
bytes are available with a granularity of four. The TLR should be programmed for N
4,
where N is the desired trigger level.
Table 20:
Transmission Control Register bits description
Bit
Symbol
Description
7-4
TCR[7:4]
RX FIFO trigger level to resume transmission (0-60).
3-0
TCR[3:0]
RX FIFO trigger level to halt transmission (0-60).
Table 21:
Trigger Level Register bits description
Bit
Symbol
Description
7-4
TLR[7:4]
RX FIFO trigger levels (4-60), number of characters available.
3-0
TLR[3:0]
TX FIFO trigger levels (4-60), number of spaces available.
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