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| 型號： | 935270053518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 657K |
| 代理商： | 935270053518 |
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Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
13 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.6 DMA operation
The SC16C750 FIFO trigger level provides additional exibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
Table 5:
Baud rates using 1.8432 MHz or 3.072 MHz crystal
Using 1.8432 MHz crystal
Using 3.072 MHz crystal
Desired
baud rate
Divisor for
16
× clock
Baud rate
error
Desired
baud rate
Divisor for
16
× clock
Baud rate
error
50
2304
50
3840
75
1536
75
2560
110
1047
0.026
110
1745
0.026
134.5
857
0.058
134.5
1428
0.034
150
768
150
1280
300
384
300
640
600
192
600
320
1200
96
1200
160
1800
64
1800
107
0.312
2000
58
0.69
2000
96
2400
48
2400
80
3600
32
3600
53
0.628
4800
24
4800
40
7200
16
7200
27
1.23
9600
12
9600
20
19200
6
19200
10
38400
3
38400
5
56000
2
2.86
Table 6:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 7:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO
0-to-1 transition when FIFO becomes full
0 = FIFO empty
1-to-0 transition when FIFO goes below trigger level
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