
Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
21 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C750 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0110
LSR (Receiver Line Status Register)
2
0100
RXRDY (Received Data Ready)
2
1100
RXRDY (Receive Data time-out)
3
0010
TXRDY (Transmitter Holding Register
Empty)
4
0000
MSR (Modem Status Register)
Table 13:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5
ISR[5]
64-byte FIFO enable.
Logic 0 = 16-byte operation.
Logic 1 = 64-byte operation.
4
ISR[4]
Not used.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
Table 12).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).