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參數(shù)資料
| 型號： | 935270053512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 45/48頁 |
| 文件大?。?/td> | 657K |
| 代理商： | 935270053512 |
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Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
6 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CS0, CS1,
CS2
14, 15,
16
59, 61, 62
I
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these three
inputs select the UART. When any of these inputs are inactive, the UART
remains inactive (refer to AS description).
CTS
40
33
I
Clear to send. CTS is a modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (
CTS) of the
modem status register indicates that CTS has changed states since the last
read from the modem status register. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not enabled,
an interrupt is generated. CTS is also used in the auto-CTS mode to control
the transmitter.
D7-D0
2-9
52, 51, 50,
48, 46, 45,
43, 42
I/O
Data bus. Eight data lines with 3-State outputs provide a bi-directional path
for data, control and status information between the UART and the CPU.
DCD
42
36
I
Data carrier detect. DCD is a modem status signal. Its condition can be
checked by reading bit 7 (DCD) of the modem status register. Bit 3 (
DCD)
of the modem status register indicates that DCD has changed states since
the last read from the modem status register. If the modem status interrupt
is enabled when DCD changes levels, an interrupt is generated.
DDIS
26
12
O
Driver disable. DDIS is active (LOW) when the CPU is not reading data.
When active, DDIS can disable an external transceiver.
DSR
41
35
I
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1 (
DSR)
of the modem status register indicates DSR has changed levels since the
last read from the modem status register. If the modem status interrupt is
enabled when DSR changes levels, an interrupt is generated.
DTR
37
28
O
Data terminal ready. When active (LOW), DTR informs a modem or data
set that the UART is ready to establish communication. DTR is placed in the
active level by setting the DTR bit of the modem control register. DTR is
placed in the inactive level either as a result of a Master Reset, during loop
mode operation, or clearing the DTR bit.
INT
33
23
O
Interrupt. When active (HIGH), INT informs the CPU that the UART has an
interrupt to be serviced. Four conditions that cause an interrupt to be issued
are: a receiver error, received data that is available or timed out (FIFO mode
only), an empty transmitter holding register or an enabled modem status
interrupt. INT is reset (deactivated) either when the interrupt is serviced or
as a result of a Master Reset.
MR
39
32
I
Master Reset. When active (HIGH), MR clears most UART registers and
sets the levels of various output signals.
NC
34
3, 5, 7, 11,
14, 16, 19,
22, 24, 27,
29, 31, 34,
37, 39, 41,
44, 47, 49,
53, 56, 57,
60, 63
Not connected.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP64
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