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參數(shù)資料
| 型號： | 935267395557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PBGA156 |
| 封裝： | 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156 |
| 文件頁數(shù)： | 149/178頁 |
| 文件大?。?/td> | 988K |
| 代理商： | 935267395557 |
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2004 Jul 22
72
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
9.4.3
ERASING CONDITIONS
The status flags are grouped into four 8-bit registers.
The interrupt flag will only be cleared on a read access to
the status register in which the signal is located which
caused the interrupt. This implies that it is sufficient to clear
the interrupt by reading only those registers which have
been enabled by their corresponding masks.
Priority: If a new trigger condition occurs at the SAME time
(clock) on which a status is being read, the flag will NOT
be cleared.
9.5
Video expansion port (X port)
The expansion port is intended for transporting video
streams image data from other digital video circuits such
as MPEG encoder/decoder and video phone codec, to the
image port (I port).
The expansion port consists of two groups of signals/pins:
8-bit data, I/O, regularly components video Y-C
B-CR
4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw
video samples (e.g. ADC test). In input mode the data
bus can be extended to 16-bit by pins HPD7 to HPD0.
Clock, synchronization and auxiliary signals,
accompanying the data stream, I/O.
As output, these are direct copies of the decoder signals.
The data transfers through the expansion port represent a
single D1 port, with half duplex mode. The SAV and EAV
codes may be inserted optionally for data input (controlled
by bit XCODE[92H[3]]). The input/output direction is
switched for complete fields only.
Table 28 Signals dedicated to the expansion port
Note
1. Pin numbers for QFP160 in parenthesis.
SYMBOL
PIN(1)
I/O
DESCRIPTION
BIT
XPD7 to
XPD0
C11, A11, B10, A10,
B9, A9, B8 and A8
(127, 128, 130, 131,
134, 135, 138 and 139)
I/O X port data: in output mode controlled by decoder section,
serial input data or luminance part of a 16-bit
Y-CB-CR 4 : 2 : 2 input
OFTS[2:0]
13H[2:0],
91H[7:0] and
C1H[7:0]
XCLK
A7 (143)
I/O clock at expansion port: if output, then copy of LLC;
as input normally a double pixel clock of up to 32 MHz or a
gated clock (clock gated with a qualier)
XCKS[92H[0]]
XDQ
B7 (144)
I/O data valid ag of the expansion port input (qualier):
if output, then decoder (HREF and VGATE) gate (see
XRDY
A6 (146)
O
data request ag = ready to receive, to work with optional
buffer in external device, to prevent internal buffer
overow;
second function: input related task ag A/B
XRQT[83H[2]]
XRH
C7 (141)
I/O horizontal reference signal for the X port:
as output: HREF or HS from the decoder (see Fig.30);
as input: a reference edge for horizontal input timing and a
polarity for input eld ID detection can be dened
XRHS[13H[6]],
XFDH[92H[6]]
and
XDH[92H[2]]
XRV
D8 (140)
I/O vertical reference signal for the X port:
as output: V123 or eld ID from the decoder,
as input: a reference edge for vertical input timing and for
input eld ID detection can be dened
XRVS[1:0]
13H[5:4],
XFDV[92H[7]]
and XDV[1:0]
92H[5:4]
XTRI
B11 (126)
I
port control: switches X port input 3-state
XPE[1:0]
83H[1:0]
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