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參數(shù)資料
| 型號： | 935266783518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 36 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114 |
| 封裝： | 16 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-537-1, LFBGA-114 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 935266783518 |
2000 Mar 16
2
Philips Semiconductors
Product specication
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
FEATURES
3-state non-inverting outputs for bus oriented
applications
Wide supply voltage range of 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A
Current drive ±24 mA at 3.0 V
Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
CMOS low power consumption
Direct interface with TTL levels
All inputs have bus-hold circuitry
Output drive capability 50 transmission lines at 85 °C
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74ALVCH32501 is a high-performance CMOS
product designed for VCC operation at 2.5 and 3.3 V with
I/O compatibility up to 5 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CPAB and CPBA).
For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When input LEAB is
LOW, the A data is latched if input CPAB is held at a HIGH
or LOW level. If input LEAB is LOW, the A data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When input OEAB is HIGH, the outputs are active. When
input OEAB is LOW, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OEBA, LEBA and CPBA. The output enables are
complimentary (OEAB is active HIGH, and OEBA is active
LOW).
To ensure the high-impedance state during power-up or
power-down, pin OEBA should be tied to VCC through a
pull-up resistor and pin OEAB should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
tPHL/tPLH
propagation delay An to Bn;Bn to An
CL = 30 pF; VCC = 2.5 V
2.8
ns
CL = 50 pF; VCC = 3.3 V
3.0
ns
CI
input capacitance
4.0
pF
CI/O
input/output capacitance
8.0
pF
CPD
power dissipation capacitance per latch
VI = GND to VCC; note 1
outputs enabled
21
pF
outputs disabled
3
pF
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