
2000 Mar 16
8
Philips Semiconductors
Product specication
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
AC CHARACTERISTICS
GND = 0 V
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 40 to +85 °C
UNIT
WAVEFORMS
CL
MIN.
TYP.
MAX.
VCC = 2.3 to 2.7 V; tr =tf ≤ 2.0 ns; note 1
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 30 pF
1.0
2.8
5.1
ns
nLEBA to nAn; nLEAB to nBn
see Figs 5 and 8
1.1
3.5
6.1
ns
nCPBA to nAn; nCPAB to nBn
see Figs 5 and 8
1.0
3.3
6.1
ns
tPZH/tPZL
3-state output enable time nOEAB to nBn
see Figs 6 and 8
1.0
2.5
5.8
ns
3-state output enable time nOEBA to nAn
see Figs 6 and 8
1.3
2.8
6.3
ns
tPHZ/tPLZ
3-state output disable time nOEAB to nBn
see Figs 6 and 8
1.5
2.5
6.2
ns
3-state output disable time nOEBA to nAn
see Figs 6 and 8
1.3
2.5
5.3
ns
tW
nLEAB or nLEBA pulse width HIGH
see Figs 5 and 8
3.3
0.8
ns
nCPAB or nCPBA pulse width
HIGH or LOW
see Figs 5 and 8
3.3
2.0
ns
tsu
set-up time
nAn before nCPAB↑ or nBn before nCPBA↑
see Figs 7 and 8
1.7
0.1
ns
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA↓
see Figs 7 and 8
1.1
0.1
ns
th
hold time
nAn after nCPAB↑ or nBn after nCPBA↑
see Figs 7 and 8
1.7
0.3
ns
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA↓
see Figs 7 and 8
1.6
0.3
ns
fmax
maximum clock frequency
see Figs 5 and 8
150
330
MHz
VCC = 2.7 V; tr =tf ≤ 2.5 ns; note 2
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 50 pF
3.0
4.6
ns
nLEBA to nAn; nLEAB to nBn
see Figs 5 and 8
3.6
5.3
ns
nCPBA to nAn; nCPAB to nBn
see Figs 5 and 8
3.4
5.6
ns
tPZH/tPZL
3-state output enable time nOEAB to nBn
see Figs 6 and 8
2.7
5.3
ns
3-state output enable time nOEBA to nAn
see Figs 6 and 8
3.3
6.0
ns
tPHZ/tPLZ
3-state output disable time nOEAB to nBn
see Figs 6 and 8
3.6
5.7
ns
3-state output disable time nOEBA to nAn
see Figs 6 and 8
3.3
4.6
ns
tW
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8
3.3
0.7
ns
pulse width nCPAB or nCPBA
HIGH or LOW
see Figs 5 and 8
3.3
1.4
ns