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| 型號： | 935263158557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 52/67頁 |
| 文件大?。?/td> | 516K |
| 代理商： | 935263158557 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
56
11.
AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10% (EBx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency)
VDD = 5 V ± 10% (EFx), VSS = 0 V, tCLK min = 1/fmax (maximum operating frequency)
Tamb = 0 °C to +70 °C, tCLK min = 63 ns for P8xC557E6EBx
Tamb = –40 °C to +85 °C, tCLK min = 63 ns for P8xC557E6EFx
C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified.
12MHz CLOCK
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/tCLK
53
System clock frequency
3.5
16
MHz
tLHLL
53
ALE pulse width
127
85
2tCLK–40
ns
tAVLL
53
Address valid to ALE LOW
43
23
tCLK–40
ns
tLLAX
53
Address hold after ALE LOW
53
33
tCLK–30
ns
tLLIV
53
ALE LOW to valid instruction in
234
150
4tCLK–100
ns
tLLPL
53
ALE LOW to PSEN LOW
53
33
tCLK–30
ns
tPLPH
53
PSEN pulse width
205
143
3tCLK–45
ns
tPLIV
53
PSEN LOW to valid instruction in
145
83
3tCLK–105
ns
tPXIX
53
Input instruction hold after PSEN
0
ns
tPXIZ
53
Input instruction float after PSEN
59
38
tCLK–25
ns
tAVIV
53
Address to valid instruction in
312
208
5tCLK–105
ns
tPLAZ
53
PSEN LOW to address float
10
ns
Data Memory
tAVLL
54, 55
Address valid to ALE LOW
43
23
tCLK–40
ns
tLLAX
54, 55
Address hold after ALE LOW
48
28
tCLK–35
ns
tRLRH
54
RD pulse width
400
275
6tCLK–100
ns
tWLWH
55
WR pulse width
400
275
6tCLK–100
ns
tRLDV
54
RD LOW to valid data in
252
148
5tCLK–165
ns
tRHDX
54
Data hold after RD
0
ns
tRHDZ
54
Data float after RD
97
55
2tCLK–70
ns
tLLDV
54
ALE LOW to valid data in
517
350
8tCLK–150
ns
tAVDV
54
Address to valid data in
585
398
9tCLK–165
ns
tLLWL
54, 55
ALE LOW to RD or WR LOW
200
300
138
238
3tCLK–50
3tCLK+50
ns
tAVWL
54, 55
Address valid to WR LOW or RD LOW
203
120
4tCLK–130
ns
tQVWX
55
Data valid to WR transition
33
13
tCLK–50
ns
tQVWH
55
Data before WR
433
288
7tCLK–150
ns
tWHQX
55
Data hold after WR
33
13
tCLK–50
ns
tRLAZ
54
RD low to address float
0
ns
tWHLH
54, 55
RD or WR HIGH to ALE HIGH
43
123
23
103
tCLK–40
tCLK+40
ns
UART Timing – Shift Register Mode (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80pF)
tXLXL
57
Serial port clock cycle time
1.0
0.75
12tCLK
s
tQVXH
57
Output data setup to clock rising edge
700
492
10tCLK–133
ns
tXHQX
57
Output data hold after clock rising edge
50
8
2tCLK–117
ns
tXHDX
57
Input data hold after clock rising edge
0
ns
tXHDV
57
Clock rising edge to input data valid
700
492
10tCLK–133
ns
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