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參數(shù)資料
| 型號： | 935262403118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封裝： | 3 MM, PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 711K |
| 代理商： | 935262403118 |
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Philips Semiconductors
PCF8563
Real-time clock/calendar
Product specication
16 April 1999
19 of 30
9397 750 04855
Philips Electronics N.V. 1999. All rights reserved.
11. Dynamic characteristics
[1]
Unspecied for fCLKOUT = 32.768 kHz.
[2]
All timing values are valid within the operating supply voltage range at Tamb and referenced to VIL and VIH with an input voltage swing of
VSS to VDD.
[3]
I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
Table 30: Dynamic characteristics
VDD = 1.8 to 5.5 V; VSS =0V; Tamb = 40 to +85 °C; fOSC = 32.768 kHz; quartz Rs =40k; CL = 8 pF; unless otherwise
specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator
CL(integrated) integrated load capacitance
15
25
35
pF
fOSC/fOSC oscillator stability
V
DD = 200 mV; Tamb =25 °C
2
× 107
Quartz crystal parameters (fOSC = 32.768 kHz)
Rs
series resistance
40
k
CL
parallel load capacitance
10
pF
CT
trimmer capacitance
5
25
pF
CLKOUT output
δCLKOUT
CLKOUT duty factor
50
%
fSCL
SCL clock frequency
400
kHz
tHD;STA
START condition hold time
0.6
s
tSU;STA
set-up time for a repeated
START condition
0.6
s
tLOW
SCL LOW time
1.3
s
tHIGH
SCL HIGH time
0.6
s
tr
SCL and SDA rise time
0.3
s
tf
SCL and SDA fall time
0.3
s
Cb
capacitive bus line load
400
pF
tSU;DAT
data set-up time
100
ns
tHD;DAT
data hold time
0
ns
tSU;STO
set-up time for STOP condition
4.0
s
tSW
tolerable spike width on bus
50
ns
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