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參數(shù)資料
| 型號： | 935262009118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AH, SOT-341-1, SSOP-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 935262009118 |
Philips Semiconductors
Product specification
PCK2000M
CK97 (66/100MHz) Mobile System Clock Generator
1998 Sep 29
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
26
REF
14.318 MHz clock output
28
VSSREF
GROUND for REF output
27
VDDREF
POWER for REF output
1
XTAL_IN
14.318 MHz crystal input
2
XTAL_OUT
14.318 MHz crystal output
3, 12
VSSPCI [0–1]
GROUND for PCI outputs
4
PCICLK_F
Free-running PCI output
6, 9
VDDPCI [0–1]
POWER for PCI outputs
5, 7, 8, 10, 11
PCICLK [1–5]
PCI clock outputs.
13, 21
VDDCORE [0–1]
Isolated POWER for core
14, 20
VSSCORE [0–1]
Isolated GROUND for core
16
SEL
Logic select pins
15
SEL100/66
Select pin for enabling 66 MHz or 100MHz or 66 MHz. L = 66 Mhz
H = 100MHz
17
PWRDWN
Control pin to put device in powerdown state, active low
18
CPUSTOP
Control pin to disable CPU clocks, active low
19
PCISTOP
Control pin to disable PCI clocks, active low
25
VDDCPU
Power for CPU outputs
22
VSSCPU
GROUND for CPU outputs
23, 24
CPUCLK [0–1]
CPU and Host clock outputs 2.5V
NOTE:
1. VDD and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the VDDCPU pins tied to a 2.5V supply, all remaining VDD pins
tied to a common 3.3V supply and all VSS pins being common.
BLOCK DIAGRAM
PWRDWN
LOGIC
STOP
LOGIC
STOP
LOGIC
PLL1
14.318
MHZ
OSC
PWRDWN
LOGIC
SW00275
X
REFCLK (14.318 MHz)
PWRDWN
PCISTOP
CPUSTOP
SEL0
SEL100/66
XTAL_IN
XTAL_OUT
CPUCLK [0–1]
PCICLK_F (33MHz)
PCICLK [1–5] (33MHz)
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