
Philips Semiconductors
Product specification
PCK2000M
CK97 (66/100MHz) Mobile System Clock Generator
1998 Sep 29
7
AC CHARACTERISTICS
VDDREF = VDDPCI (0–1)= 3.3V
± 5%; VDDCPU = 2.5V ± 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = 0°C to +70°C
UNIT
NOTES
MIN
MAX
THKP (tP)
CPUCLK period
2
15.0
15.5
THKH (tH)
CPUCLK HIGH time
66MHz
1, 5
5.2
ns
THKL (tL)
CPUCLK LOW time
1, 5
5.0
THKP (tP)
CPUCLK period
2
10.0
10.5
THKH (tH)
CPUCLK HIGH time
100MHz
1, 5
3.0
ns
THKL (tL)
CPUCLK LOW time
1, 5
2.8
THRISE (tR)
CPUCLK rise time
9
0.4
1.6
ns
THFALL (tF)
CPUCLK fall time
9
0.4
1.6
ns
TJITTER (tJC)
CPUCLK jitter
175
ps
DUTY CYCLE (tD)
Output Duty Cycle
1
45
55
%
THSKW (tSK)
CPU Bus CLK skew
2
175
ps
THSTB (fST)
CPUCLK stabilization from Power-up
7
3
ms
PCI CLOCK OUTPUTS, PCI(1–5) AND PCI_F (LUMP CAPACITANCE TEST LOAD = 30pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = 0°C to +70°C
UNIT
NOTES
MIN
MAX
TPKP (tP)
PCICLK period
3
30.0
ns
TPKPS
PCICLK period stability
8
500
ps
TPKH (tH)
PCICLK HIGH time
1
12.0
ns
TPKL (tL)
PCICLK LOW time
1
12.0
ns
THRISE (tR)
PCICLK rise time
10
0.5
2.0
ns
THFALL (tF)
PCICLK fall time
10
0.5
2.0
ns
TPSKW (tSK)
PCI Bus CLK skew
2
500
ps
THPOFFSET (tO)
CPUCLK to PCICLK Offset
2, 4
1.5
4.0
ns
TPSTB (fST)
PCICLK stabilization from Power-up
7
3
ms
REF CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = 0°C to +70°C
UNIT
NOTES
MIN
MAX
f
Frequency, Actual
Frequency generated
by Crystal
14.31818
MHz
THRISE (tR)
Output rise edge rate
1
4
ns
THFALL (tF)
Output fall edge rate
1
4
ns
DUTY CYCLE (tD)
Duty Cycle
45
55
%
THSTB (fST)
Frequency stabilization from Power-up (cold start)
3
ms