參數(shù)資料
型號(hào)： 935261617118
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 24-BIT DAC, PDSO32
封裝： 7.50 MM, PLASTIC, SO-32
文件頁(yè)數(shù)： 29/31頁(yè)
文件大小： 199K
代理商： 935261617118
2000 Jan 04
7
Philips Semiconductors
Preliminary specication
Multi-channel lter DAC
UDA1328T
8
FUNCTIONAL DESCRIPTION
8.1
System clock
The UDA1328 operates in slave mode only, this means
that in all applications the system must provide the system
clock. The system frequency is selectable. The options are
256fs, 384fs, 512fs and 768fs for the L3 mode and 256fs or
384fs for the static mode. The system clock must be
frequency-locked to the digital interface signals.
It should be noted that the UDA1328 can operate from
5 to 100 kHz sampling frequency (fs). However in 768fs
mode the sampling frequency must be limited to 55 kHz.
8.2
Application modes
Operating mode can be set with the STATIC pin, either to
L3 mode (STATIC = LOW) or to the static mode
(STATIC = HIGH). See Table 1 for pin functions in the
static mode.
Table 1
Mode selection in the static mode
Notes
1. SF1 and SF0 are the Serial Format inputs (2-bit).
2. X means that the pin has no function in this mode and
can best be connected to ground.
8.3
Interpolation lter (DAC)
The digital filter interpolates from 1 to 128fs by cascading
a half-band filter and a FIR filter, see Table 2. The overall
filter characteristic of the digital filters is illustrated in Fig.3,
and the pass-band ripple is illustrated in Fig.4. Both figures
are with a 44.1 kHz sampling frequency.
Table 2
Interpolation lter characteristics
8.4
Digital silence detection
The UDA1328 can detect digital silence conditions in
channels 1 to 6, and report this via the output pin DS. This
function is implemented to allow for external manipulation
of the audio signal in the absence of program material,
such as muting or recorder control.
An active LOW output is produced at the DS pin if the
channels selected via L3 or for all channels in static mode,
carries all zeroes for at least 9600 consecutive audio
samples (equals 200 ms for fs = 48 kHz). The DS pin is
also active LOW when the output is digitally muted either
via the L3 interface or via the STATIC pin.
In static mode all channels participate in the digital silence
detection. In L3 mode control each channel can be set,
either to participate in the digital silence detection or not.
8.5
Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream DAC (FSDAC).
8.6
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post-filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.7
Static mode
The UDA1328 is set to static mode by setting the STATIC
pin HIGH. The function of 6 pins of the device now get
another function as can be seen in Table 1.
8.7.1
SYSTEM CLOCK SETTING
In static mode pin 18 (L3CLOCK) is used to select the
system clock setting. When pin 18 is LOW, the device is in
256fs mode, when pin 18 is HIGH the device is in 384fs
mode.
PIN
L3 MODE
STATIC MODE
L3CLOCK
clock select
L3MODE
SF1(1)
L3DATA
SF0(1)
MUTE
X(2)
MUTE
DEEM1
X(2)
DEEM1
DEEM0
L3ADR
DEEM0
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.02
Stop band
>0.55fs
55
Dynamic range
0 to 0.45fs
>114
DC gain
3.5
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