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參數(shù)資料
| 型號(hào)： | 935261617112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO32 |
| 封裝： | 7.50 MM, PLASTIC, SO-32 |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 199K |
| 代理商： | 935261617112 |
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2000 Jan 04
14
Philips Semiconductors
Preliminary specication
Multi-channel lter DAC
UDA1328T
9.2.2
RESET BIT
A 1-bit value to initialize the L3 registers with the default
settings (except the system clock setting and the data
input format setting) by writing a logic 1 to RST
(see Table 6).
The default settings after reset are as follows:
Mute mode: soft mute
Power: on
Volume: 0 dB
Sub volume: 0 dB
De-emphasis: off
Mute: off
Silence detect mode: detect
Polarity: non-inverting.
9.2.3
SYSTEM CLOCK FREQUENCY
A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 8).
Table 8
System clock frequency settings
9.2.4
DATA INPUT FORMAT
A 3-bit value (IF2 to IF0) to select the used data format
(see Table 9).
Table 9
Data input format settings
SC1
SC0
FUNCTION
0
512fs
0
1
384fs
1
0
256fs
1
768fs
IF2
IF1
IF0
FUNCTION
000
I2S-bus
0
1
LSB-justied; 16 bits
0
1
0
LSB-justied; 18 bits
0
1
LSB-justied; 20 bits
1
0
MSB-justied
1
0
1
LSB-justied; 24 bits
1
0
reserved
1
reserved
9.2.5
QUICK MUTE
A 1-bit value to set the mute mode to either soft mute (via
cosine roll-off), quick or hard mute.
Table 10 Quick mute
9.2.6
POWER CONTROL
A 1-bit value to disable the ADC and/or DAC to reduce
power consumption.
Table 11 Power control settings
9.3
Feature settings
In the UDA1328 there are features that can be controlled
either per-channel or all at the same time. These features
are:
Volume control
Sub volume control
Mute
Output polarity control
Digital silence detect.
When a ‘per-channel’ setting is required for these features,
the ACH bit (see Table 7) must be set to logic 0 before
writing a new value to one of the features. Once this has
been performed a channel is selected via the CH2 to CH0
bits. The features for this channel can be controlled without
sending the same channel address again (low
microcontroller mode).
When the ACH bit is set to logic 1, which means ‘a(chǎn)ll
channels select’, all channels will be set to the same value
of the feature sent afterwards.
For the digital silence detector it holds that the DS pin is
either active on the selected channel when bit ACH is set
to logic 0 before writing the DSM bit, or the DS pin is active
on all channels when the ACH bit is set to logic 1.
QM
FUNCTION
0
soft mute mode
1
quick mute mode
PC
FUNCTION
0
all channels off
1
all channels on
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