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參數(shù)資料
| 型號： | 935261617112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO32 |
| 封裝： | 7.50 MM, PLASTIC, SO-32 |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 199K |
| 代理商： | 935261617112 |
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2000 Jan 04
8
Philips Semiconductors
Preliminary specication
Multi-channel lter DAC
UDA1328T
8.7.2
DE-EMPHASIS CONTROL
In static pin mode the pins DEEM0 and DEEM1 control the
de-emphasis mode; see Table 3.
Table 3
De-emphasis control
8.7.3
DIGITAL INTERFACE FORMATS
In static pin mode the digital audio interface formats can be
selected via pin 17 (SF1) and 19 (SF0). The following
interface formats can be selected (see also Table 4):
I2S-bus with data word length of up to 24 bits
LSB-justified format with data word length of
16, 20 or 24 bits.
Table 4
Input format selection in the static mode
It should be noted that the digital audio interface holds that
the BCK frequency can be 64 times the WS maximum
frequency, or fBCK ≤ 64 × fWS
DEEM MODE
DEEM1
DEEM0
No de-emphasis
0
32 kHz de-emphasis
0
1
44.1 kHz de-emphasis
1
0
48 kHz de-emphasis
1
INPUT FORMAT
SF1
SF0
I2S-bus
0
LSB-justied 16 bits
0
1
LSB-justied 20 bits
1
0
LSB-justied 24 bits
1
8.8
L3 mode
The device is set to L3 mode by setting the STATIC pin to
LOW. The device can then be controlled via the L3
microcontroller interface (see Chapter 9).
8.8.1
DIGITAL INTERFACE FORMATS
The following interface formats can be selected in the
L3 mode:
I2S-bus with data word length of up to 24 bits
MSB-justified with data word length of up to 24 bits
LSB-justified format with data word length of 16, 18,
20 or 24 bits.
8.8.2
L3 ADDRESS
The UDA1328 can be addressed via the L3 microcontroller
interface using one of two addresses. This is done in order
to individually control the UDA1328 and other Philips
DACs or CODECs via the same L3 bus.
The address can be selected using pin 25 (DEEM0) in
L3 mode. When pin 25 is set LOW, the address is 000100.
When pin 25 is set HIGH the address is 000101.
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