參數(shù)資料
型號(hào)： 935261242112
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 20-BIT DAC, PDSO16
封裝： 4.40 MM, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 142K
代理商： 935261242112
2000 Jan 10
14
Philips Semiconductors
Preliminary specication
Low-cost stereo lter DAC
UDA1320ATS
15.2
Digital
VDDD =VDDA = 2.7 to 3.6 V; Tamb = 20 to +85 °C; RL =5k. All voltages referenced to ground (pins 5 and 15); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Tsys
system clock cycle
fsys = 256fs
78
88
244
ns
fsys = 384fs
52
59
162
ns
fsys = 512fs
39
44
122
ns
tCWL
LOW-level system clock pulse width
fsys < 19.2 MHz
30
70
%Tsys
fsys ≥ 19.2 MHz
40
60
%Tsys
tCWH
HIGH-level system clock pulse width
fsys < 19.2 MHz
30
70
%Tsys
fsys ≥ 19.2 MHz
40
60
%Tsys
Serial input data timing (see Fig.7)
Tcy(CLK)(bit)
bit clock period
300
ns
tCLKH(bit)
bit clock HIGH time
100
ns
tCLKL(bit)
bit clock LOW time
100
ns
tr
rise time
20
ns
tf
fall time
20
ns
tsu(i)(D)
data input set-up time
20
ns
th(i)(D)
data input hold time
0
ns
tsu(WS)
word selection set-up time
20
ns
th(WS)
word selection hold time
10
ns
Microcontroller interface timing (see Figs 4 and 6)
Tcy(CLK)(L3)
L3CLK
500
ns
tCLK(L3)H
L3CLK HIGH period
250
ns
tCLK(L3)L
L3CLK LOW period
250
ns
tsu(L3)A
L3MODE set-up time
addressing mode
190
ns
th(L3)A
L3MODE hold time
addressing mode
190
ns
tsu(L3)D
L3MODE set-up time
data transfer mode
190
ns
th(L3)D
L3MODE hold time
data transfer mode
190
ns
tsu(L3)DA
L3DATA set-up time
data transfer and
addressing mode
190
ns
th(L3)DA
L3DATA hold time
data transfer and
addressing mode
30
ns
tstp(L3)
L3MODE halt time
190
ns
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