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參數(shù)資料
| 型號： | 935261242112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 142K |
| 代理商： | 935261242112 |
2000 Jan 10
9
Philips Semiconductors
Preliminary specication
Low-cost stereo lter DAC
UDA1320ATS
Fig.5 Multi-byte transfer.
handbook, full pagewidth
tstp(L3)
address
L3DATA
L3CLK
L3MODE
address
data byte #1
data byte #2
MBK074
Fig.6 Timing for data transfer mode.
handbook, full pagewidth
tstp(L3)
tsu(L3)D
th(L3)DA
tsu(L3)DA
th(L3)DA
th(L3)D
MBK073
Tcy(CLK)L3
BIT 0
L3MODE
L3CLCK
L3DATA
write
BIT 7
tCLK(L3)H
tCLK(L3)L
The sound feature values are stored in independent
registers. The first selection of the registers is achieved by
the choice of data type that is transferred (‘STATUS’ or
‘DATA’ transfer). This is performed in the address mode
using bit 1 and bit 0, see Table 4,. The settings that can be
controlled with ‘STATUS’ transfer are given in table 5, and
the settings that can be controlled using ‘DATA’ transfer
are given in table 6.
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6). The other bits in the data byte
(bit 5 to bit 0) is the value that is placed in the selected
registers.
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