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參數(shù)資料
| 型號： | 935260792118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOT-340-1, SSOP-24 |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 206K |
| 代理商： | 935260792118 |
1996 Jul 30
9
Philips Semiconductors
Product specication
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Table 1
Output coding and input voltage (typical values)
Table 2
Clamping input level (VCLPR, VCLPG and VCLPB)
Note
1. Use capacitor
≥10 pF to VSSA.
Table 3
Clamp and inputs RED, GREEN and BLUE; VDDA =VDDD =VDDO =3V
Note
1. Where X = don’t care.
Table 4
Clamping characteristic related to TV signals
STEP
Vi(p-p) (V)
BINARY OUTPUT BITS
VDDA =VDDD =3V VDDA =VDDD = 5 V
D5
D4
D3
D2
D1
D0
Underow
<VDDA 1.1
<VDDA 1.06
0
0VDDA 1.1
VDDA 1.06
0
1
.
0
00001
.
.....
.
.....
62
.
111110
63
VDDA 0.4
111111
Overow
>VDDA 0.4
111111
VCLPR, VCLPG AND VCLPB
CLAMPING LEVEL
Open-circuit(1)
code 0
Vcode 9 to Vcode 20
code
9 to code 20
SR or SG or SB
CLAMP
VCLPR, VCLPG or VCLPB
Vi RED or GREEN or BLUE
DIGITAL OUTPUTS
0
1
open
VDDA 1.1 V
X(1)
VCLP
1
open
VDDA 1.1 V
0
VCLP
code (VCLP)
PARAMETER
MIN.
TYP.
MAX.
UNIT
Clamping time per line (signal active)
2.2
3.0
s
Input signals clamped to correct level
3
10
lines
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