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參數(shù)資料
| 型號： | 935260792118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOT-340-1, SSOP-24 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 206K |
| 代理商： | 935260792118 |
1996 Jul 30
6
Philips Semiconductors
Product specication
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
CHARACTERISTICS
VDDA =V5 to V7 = 2.7 to 5.5 V; VDDD =V23 to V22 = 2.7 to 5.5 V; VDDO =V21 to V14 = 2.7 to 5.5 V;
VSSA,VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = 40 to +85 °C; typical values measured at
VDDA =VDDD =VDDO = 3 V and Tamb =25 °C; unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
2.7
3.0
5.5
V
VDDD
digital supply voltage
2.7
3.0
5.5
V
VDDO
output stages supply
voltage
2.7
3.0
5.5
V
VDD
supply voltage difference
VDDA VDDD
0.3
+0.3
V
VDDA VDDO
0.3
+0.3
V
VDDD VDDO
0.3
+0.3
V
IDDA
analog supply current
710
mA
IDDD
digital supply current
46
mA
IDDO
output stages supply current fclk = 40 MHz; ramp input
1
1.5
mA
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); note 1
VIL
LOW level input voltage
0
VDDD × 0.3 V
VDDD < 3.3 V
0
VDDD × 0.2 V
VIH
HIGH level input voltage
VDDD × 0.7
VDDD
V
VDDD < 3.3 V
VDDD × 0.8
VDDD
V
IIL
LOW level input current
Vclk =VDDD × 0.2
10
+1
A
IIH
HIGH level input current
Vclk =VDDD × 0.8
210
A
Zi
input impedance
fclk = 40 MHz
4
k
CI
input capacitance
fclk = 40 MHz
3
pF
INPUTS SR, SG, SB, CLP (REFERENCED TO VSSD)
VIL
LOW level input voltage
0
VDDD × 0.3 V
VDDD < 3.3 V
0
VDDD × 0.2 V
VIH
HIGH level input voltage
VDDD × 0.7
VDDD
V
VDDD < 3.3 V
VDDD × 0.8
VDDD
V
IIL
LOW level input current
VIL =VDDD × 0.2
1
A
IIH
HIGH level input current
VIH =VDDD × 0.8
+1
A
INPUTS VCLPR,VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2
VCLP
input voltage for clamping
Vcode 9
Vcode 20
V
ICLP
input current
30
A
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