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參數(shù)資料
| 型號(hào)： | 935260792118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOT-340-1, SSOP-24 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 206K |
| 代理商： | 935260792118 |
1996 Jul 30
7
Philips Semiconductors
Product specication
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
ANALOG INPUTS RED, GREEN AND BLUE; see Table 1
Vi(p-p)
input voltage amplitude
(peak-to-peak value)
VDDA =VDDD =3V;
Tamb =25 °C
0.665
0.70
0.735
V
VDDA =VDDD =5V;
Tamb =25 °C
0.625
0.66
0.695
V
Ii
input current
10
A
Cclamp
clamp coupling capacitance
1
10
100
nF
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
VDDA =3V
VDDA 1.19
V
VDDA =5V
VDDA 1.13
V
TVRB
temperature variation on
VRB
Tamb = 0 to 50 °C
0.7
mV/
°C
Outputs
DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD)
VOL
LOW level output voltage
IO = 1 mA
0
0.5
V
VOH
HIGH level output voltage
IO = 1mA
VDDO 0.5
VDDO
V
Switching characteristics
CLOCK INPUT CLK; see Fig.3; note 1
fclk(max)
maximum clock frequency
40
MHz
fmux(max)
maximum multiplexer
frequency
20
MHz
tCPH
clock pulse width HIGH
8
ns
tCPL
clock pulse width LOW
8
ns
tr
clock rise time
10% to 90%; fclk ≤ 25 MHz;
LOW=VSSD, HIGH = VDDD
10
ns
tf
clock fall time
90% to 10%; fclk ≤ 25 MHz;
LOW=VSSD, HIGH = VDDD
10
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input;
Tamb =25 °C
±0.25
±0.6
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input;
Tamb =25 °C
±0.20
±0.5
LSB
EFFECTIVE BITS; note 2
EB
effective bits
fclk = 40 MHz; fi = 4.43 MHz
5.8
bits
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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