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參數(shù)資料
| 型號： | 935260736112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 935260736112 |
2002 Jun 18
9
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
AC WAVEFORMS
handbook, full pagewidth
MNA422
th
tsu
th
tPHL
tW
tPLH
tsu
1/fmax
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.6
The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
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