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參數(shù)資料
| 型號： | 935260736112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 935260736112 |
2002 Jun 18
8
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
AC CHARACTERISTICS
GND = 0 V; tr =tf ≤ 2.5 ns.
Notes
1. Typical values are measured at VCC = 3.3 V.
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
SYMBOL
PARAMETER
WAVEFORMS
Tamb (°C)
UNIT
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
VCC = 1.2 V
tPHL/tPLH
propagation delay nCP to nQ, nQ
see Figs 6 and 8
15
ns
propagation delay nSD to nQ, nQ
see Figs 7 and 8
15
ns
propagation delay nRD to nQ, nQ
see Figs 7 and 8
15
ns
VCC = 2.7 V
tPHL/tPLH
propagation delay nCP to nQ, nQ
see Figs 6 and 8
1.0
2.7
6.0
1.0
7.5
ns
propagation delay nSD to nQ, nQ
see Figs 7 and 8
1.0
3.2
6.4
1.0
8.0
ns
propagation delay nRD to nQ, nQ
see Figs 7 and 8
1.0
3.2
6.4
1.0
8.0
ns
tW
clock pulse width HIGH or LOW
see Figs 6 and 8
3.3
4.5
ns
set or reset pulse width LOW
see Figs 7 and 8
3.3
4.5
ns
trem
removal time set or reset
see Figs 7 and 8
1.5
1.5
ns
tsu
set-up time nD to nCP
see Figs 6 and 8
2.2
2.2
ns
th
hold time nD to nCP
see Figs 6 and 8
1.0
1.0
ns
fmax
maximum clock pulse frequency
see Figs 6 and 8
83
66
MHz
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay nCP to nQ, nQ
see Figs 6 and 8
1.0
2.5
5.2
1.0
6.5
ns
propagation delay nSD to nQ, nQ
see Figs 7 and 8
1.0
2.5
5.4
1.0
7.0
ns
propagation delay nRD to nQ, nQ
see Figs 7 and 8
1.0
2.5
5.4
1.0
7.0
ns
tW
clock pulse width HIGH or LOW
see Figs 6 and 8
3.3
1.3
4.5
ns
set or reset pulse width LOW
see Figs 7 and 8
3.3
1.7
4.5
ns
trem
removal time set or reset
see Figs 7 and 8
1.0
3.0
1.0
ns
tsu
set-up time nD to nCP
see Figs 6 and 8
2.0
0.8
2.0
ns
th
hold time nD to nCP
see Figs 6 and 8
0.0
0.7
0.0
ns
fmax
maximum clock pulse frequency
see Figs 6 and 8
150
250
120
MHz
tsk(0)
skew
note 2
1.0
1.5
ns
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