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參數(shù)資料
| 型號： | 935260736112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 935260736112 |
2002 Jun 18
10
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
handbook, full pagewidth
MNA423
trem
tPHL
tW
tPLH
VM
tW
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.7
The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRD to nCP removal time.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
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