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參數(shù)資料
| 型號： | 935260531512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 47/67頁 |
| 文件大?。?/td> | 400K |
| 代理商： | 935260531512 |
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1998 Apr 07
51
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
Notes
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr =tf = 5 ns;
VIL =VSS + 0.5 V; VIH =VDD 0.5 V; XTAL2 not connected; EA = RST = Port 0 = VDD; the Watchdog Timer is
disabled (by the external reset).
2. IDD(max) at other frequencies can be derived from Fig.28.
3. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr =tf = 5 ns;
VIL =VSS +0.5 V; VIH =VDD 0.5 V; XTAL2 not connected; the Watchdog Timer is disabled; EA = RST = VSS;
Port 0 = P1.6 = P1.7 = VDD.
4. The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Watchdog Timer is
disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD.
5. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW-level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading
>100 pF) the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to provide ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per port pin: 10 mA.
b) Maximum IOL per 8-bit port: Port 0 = 26 mA; Ports 1, 2, 3, 4 and5=15mA.
c) Maximum total IOL for all output pins: 71 mA.
d) If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
7. Capacitive loading on Port 0 and Port 2 may cause the HIGH-level output voltage on ALE and PSEN to momentarily
fall below the 0.9VDD specification when the address bits are stabilizing.
VOH1
HIGH level output voltage
Port 0 in external bus mode,
ALE, PSEN and RST
IOH = 800 A; VDD =5V ±10%
2.4
V
IOH = 300 A
0.75VDD
V
IOH = 80 A; note 7
0.9VDD
V
RRST
RST pull
down resistor
40
100
k
CI/O
capacitance of input buffer
test frequency = 1 MHz;
Tamb =25 °C
10
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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