
1998 Apr 07
38
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
Notes
1. VDD must be applied before VPP and removed after VPP.
2. VPP must not exceed 14 V including overshoot.
3. The device reliability can be affected when the device is installed or removed while VPP =12V.
4. Do not alter VPP either ‘VIL to 12 V’ or ‘12 V to VIL’ when CE = VIL.
5. VIL(min) = 0.5 V for pulse width < 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
Table 28 AC characteristics during command programming, data programming and erase operation
Tamb = 0 to 70 °C; VDD =5V+ 10%; VPP = 12 V + 5%; refer to Figs 23 to 27.
IDD(erase)
supply current erase mode
50
mA
IDD(prog-verify)
supply current program/verify mode
50
mA
IDD(erase-verify)
supply current erase/verify mode
50
mA
IPP(read)
programming supply current read
mode
VPP = 12.6 V; note 2 and 3
100
A
IPP(prog)
programming supply current
program mode
50
mA
IPP(erase)
programming supply current erase
mode
50
mA
IPP(prog-verify)
programming supply current
programming/erase mode
50
mA
IPP(erase-verify)
programming supply current
erase/verify mode
50
mA
VIL
LOW-level input voltage
note 4
0.5(5)
0.2VPP 0.3 V
VIH
HIGH-level input voltage
2.4
VDD + 0.3(6)
V
VOL
LOW-level output voltage
IOL = 2.1 mA
0.45
V
VOH
HIGH-level output voltage
IOH = 400 A
2.4
V
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
tsu(Vpp)
VPP set-up time
100
ns
tsu(OE)
OE set-up time
100
ns
Tcy(P)
command programming cycles
150
ns
tWP(WE)
WE programming pulse width
60
ns
tWP(WE)H1
WE programming pulse width HIGH
20
ns
tWP(WE)H2
WE programming pulse width HIGH
100
ns
tsu(A)
address set-up time
0
ns
th(A-DATA)
address hold time for DATA polling
0
ns
tsu(D)
DATA set-up time
50
ns
th(D)
DATA hold time
10
ns
tsu(DATA-CE)
CE set-up time before DATA polling/toggle bit
100
ns
tsu(CE)
CE set-up time
0
ns
tsu(CE-W)
CE set-up time before command write
100
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT