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參數(shù)資料
| 型號： | 935260531512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 33/67頁 |
| 文件大?。?/td> | 400K |
| 代理商： | 935260531512 |
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1998 Apr 07
39
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
Notes
1. CE and OE must be fixed HIGH during VPP transition from ‘5 to 12 V’ or from ‘12 to 5 V’.
2. to(dis) defined as the time at which the output achieves the open circuit condition and data is no longer driven.
th(Vpp)
VPP hold time
100
ns
to(dis)
output disable time; note 2
35
ns
tACC(DATA)
DATA polling/toggle bit access time
150
ns
tE(tot)
total erase time in auto-chip-erase
5
s
tP(tot)
total programming time in auto-verify
15
300
us
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
16.12.1 AUTOMATIC PROGRAMMING
One byte data is programmed. Verifying in fast algorithm
and additional programming by external control are not
required because these operations are executed
automatically by the internal control circuit. Programming
completion can be verified by DATA polling (see
Section 16.9.2) and toggle bit (see Section 16.9.1)
checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming
on Q7. Q0 to Q5 are in high-impedance state; Q6 is the
toggle bit (see Section 16.9.1).
Figure 23 shows the timing waveform.
16.12.2 AUTOMATIC ERASE
All the data on the chip is erased. External erase verifying
is not required because data is erased automatically by
internal control circuit. Erasure completion can be verified
by DATA polling and toggle bit checking after automatic
erase starts.
Device outputs a logic 0 during erasure and a logic 1 after
erasure on Q7. Q0 to Q5 are in high-impedance state; Q6
is the toggle bit (see Section 16.9.1).
Figure 24 shows the timing waveform.
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