- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36335 > 935247890551 (NXP SEMICONDUCTORS) PICTURE-IN-PICTURE IC, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | 935247890551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 228K |
| 代理商： | 935247890551 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
1996 Aug 07
20
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9077H
The MPAL and SPAL bits set the acquisition area. When
set to logic 1 the acquisition area is enlarged from
228 lines/field (NTSC) to 276 lines/field (PAL).
The MVRPN and SVRPN bits determine the number of
repeated PIP rows. There is always one row visible of each
channel. If no PIPs should be visible the PIP channel must
be switched off (SA 00, bit 7 or bit 6).
SA 21H AND SA 2AH: HORIZONTAL REPETITION OFFSET
REGISTERS FOR ROW
0 TO 3
The horizontal repetition offsets (MHRPO and SHRPO)
are strongly related to the horizontal distance (MHDIS and
SHDIS bits). These bits set for each row a certain grid of
possible starting points for the PIPs in that row. Every grid
point has a number 0 (the most left PIP), 1, 2 or 3.
The SHRPO and MHRPO bits determine the first grid
number which will be displayed. This mechanism can be
set for each row.
SA 22H AND SA 2BH: HORIZONTAL REPETITION NUMBER
REGISTERS FOR ROW
0 TO 3
The horizontal repetition numbers (MHRPO and SHRPO)
determine how many times the PIPs are repeated in a row,
once the first PIP is displayed. The repeated PIPs stay in
the grid determined by the SHDIS and MHDIS bits for that
row. This mechanism can be set for each row
independently.
SA 23H AND SA 24H; SA 2CH AND SA 2DH: PICTURE SIZE
REGISTERS
The MHPIC and SHPIC bits determine the horizontal PIP
size in 256 steps of 4 pixels. The MVPIC and SVPIC bits
determine the vertical PIP size line in 256 steps of 1 line
for NTSC or 256 steps of 2 lines for PAL.
SA 25H TO SA 29H; SA 2EH TO SA 32H: PICTURE
DISTANCE REGISTERS
For each row the distance between starting points of PIPs
can be set with the MHDIS and SHDIS bits in 256 steps of
4 pixels. The distance between two rows can be set with
the MVDIS and SVDIS bits in 256 steps of 1 line.
Acquisition channel ADCs
Both channels convert the analog input signals to digital
signals by means of two ADCs for each channel.
The internal input levels of the ADCs of each channel are
equal and can be set by the AVrefT and AVrefB pins.
The reference levels are made internally by means of a
resistor network which divides the analog voltage to a
default set of preferred levels. External capacitors are
needed to filter AC components on the reference levels.
The resolution of the ADCs is 8-bit; Differential
Non-Linearity (DNL) is 7-bit; Integral Non-Linearity (INL) is
6-bit, and the sampling is done at the system frequency of
27 MHz for the Y-input. The U/V inputs are multiplexed
and sampled at 13.5 MHz. The analog input signals are
amplified to make maximum use of the dynamic range of
the ADCs. A bias voltage Vbias is used for decoupling AC
components on internal references. The inputs should be
AC-coupled and an internal clamp circuit will clamp the
input to AVrefB for the luminance channels and to
for the chrominance channels.
The clamping starts at the leading edge of the burst key
pulse.
Output DACs
The digitally processed signals are converted to analog
signals by means of three 8-bit DACs. The output voltages
of these DACs are default set by the DAVrefT pin for the top
level and DAVrefB pin for the bottom level. Default values
are 1.5 V.
External memory
For the external memory two VDRAMs of type Mitsubishi
M5M442256 are foreseen. They have a storage capacity
of 262144 words of 4-bit each and will be used in parallel.
It is also possible to use one 2 Mbit VDRAM of
262144 words of 8-bit. An overview of the timing diagrams
is given in Fig.9.
AV
refT
AV
refB
–
2
-----------------------------------------
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935247890557 | PICTURE-IN-PICTURE IC, PQFP100 |
| 935249180112 | 12 W, 4 CHANNEL, AUDIO AMPLIFIER, PZIP17 |
| 935251700112 | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 935251700118 | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 935251700512 | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
| 9-3525-012 | 制造商:KEYSTONE 功能描述:MODIFIED 3525,VERSION E |
| 935252-5 | 制造商:C-H 功能描述:935252-5 |
| 935257650112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY ICSUBS TO 935257650112 |
| 935260093112 | 制造商:NXP Semiconductors 功能描述:IC AVIC ADV BASESTATION 14SOIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。