參數(shù)資料
型號: 935246150005
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
封裝: CHIP ON WAFER
文件頁數(shù): 33/68頁
文件大?。?/td> 234K
代理商: 935246150005
2000 Jan 04
39
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.4.13
TRANSMIT BUFFER
The global layout of the transmit buffer is shown in Fig.7.
One has to distinguish between the Standard Frame
Format (SFF) and the Extended Frame Format (EFF)
configuration. The transmit buffer allows the definition of
one transmit message with up to eight data bytes.
6.4.13.1
Transmit buffer layout
The transmit buffer layout is subdivided into descriptor and
data fields where the first byte of the descriptor field is the
frame information byte (frame information). It describes
the frame format (SFF or EFF), remote or data frame and
the data length. Two identifier bytes for SFF or four bytes
for EFF messages follow. The data field contains up to
eight data bytes.
The transmit buffer has a length of 13 bytes and is located
in the CAN address range from 16 to 28.
Note, that a direct access to the transmit buffer RAM is
possible using the CAN address space from 96 to 108.
This RAM area is reserved for the transmit buffer.
The three following bytes may be used for general
purposes (CAN address 109, 110 and 111).
Fig.7 Transmit buffer layout for standard and extended frame format configurations.
a. Standard frame format.
b. Extended frame format.
handbook, full pagewidth
MGK621
CAN address
16
TX frame information
17
TX identifier 1
18
TX identifier 2
19
TX data byte 1
20
TX data byte 2
21
TX data byte 3
22
TX data byte 4
23
TX data byte 5
24
TX data byte 6
25
TX data byte 7
26
TX data byte 8
27
unused
28
unused
CAN address
16
TX frame information
17
TX identifier 1
18
TX identifier 2
19
TX identifier 3
20
TX identifier 4
21
TX data byte 1
22
TX data byte 2
23
TX data byte 3
24
TX data byte 4
25
TX data byte 5
26
TX data byte 6
27
TX data byte 7
28
TX data byte 8
6.4.13.2
Descriptor eld of the transmit buffer
The bit layout of the transmit buffer is represented in
Tables 25 to 27 for SFF and Tables 28 to 32 for EFF.
The given configuration is chosen to be compatible with
the receive buffer layout (see Section 6.4.14.1).
相關(guān)PDF資料
PDF描述
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
08NU10NU INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL
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