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| 型號(hào)： | 935246150005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC |
| 封裝： | CHIP ON WAFER |
| 文件頁數(shù)： | 22/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | 935246150005 |
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2000 Jan 04
29
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
5. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if
the original message has been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 or a transmit
interrupt has been generated.
It should be noted that a transmit interrupt is generated even if the message was aborted because the transmit buffer
status bit changes to ‘released’.
6. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic 1.
6.4.5
STATUS REGISTER (SR)
The content of the status register reflects the status of the CAN controller. The status register appears to the CPU as a
read only memory.
Table 14 Bit interpretation of the status register (SR); CAN address 2
BIT
SYMBOL
NAME
VALUE
FUNCTION
SR.7
BS
Bus Status; note 1
1
bus-off; the CAN controller is not involved in bus
activities
0
bus-on; the CAN controller is involved in bus
activities
SR.6
ES
Error Status; note 2
1
error; at least one of the error counters has
reached or exceeded the CPU warning limit
dened by the Error Warning Limit Register
(EWLR)
0
ok; both error counters are below the warning limit
SR.5
TS
Transmit Status; note 3
1
transmit; the CAN controller is transmitting a
message
0
idle
SR.4
RS
Receive Status; note 3
1
receive; the CAN controller is receiving a
message
0
idle
SR.3
TCS
Transmission Complete
Status; note 4
1
complete; last requested transmission has been
successfully completed
0
incomplete; previously requested transmission is
not yet completed
SR.2
TBS
Transmit Buffer Status;
note 5
1
released; the CPU may write a message into the
transmit buffer
0
locked; the CPU cannot access the transmit
buffer; a message is either waiting for
transmission or is in the process of being
transmitted
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935230900112 | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 06NU06NU | INNENGEWINDE BSP DREHB G 0.38 |
| 08NU06NU | INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL |
| 08NU08NU | INNENGEWINDE BSP DREHB G 0.5 |
| 08NU10NU | INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL |
相關(guān)代理商/技術(shù)參數(shù) |
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| 935252-5 | 制造商:C-H 功能描述:935252-5 |
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