參數(shù)資料
型號(hào): 935230900112
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 37/68頁
文件大?。?/td> 234K
代理商: 935230900112
2000 Jan 04
42
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
The lower the binary value of the identifier the higher the
priority. This is due to the larger number of leading
dominant bits during arbitration.
6.4.13.5
Data eld
The number of transferred data bytes is defined by the
data length code. The first bit transmitted is the most
significant bit of data byte 1 at CAN address 19 (SFF) or
CAN address 21 (EFF).
6.4.14
RECEIVE BUFFER
The global layout of the receive buffer is very similar to the
transmit buffer described in the previous section.
The receive buffer is the accessible part of the RXFIFO
and is located in the range between CAN address
16 and 28. Each message is subdivided into a descriptor
and a data field.
Fig.8 Example of the message storage within the RXFIFO.
handbook, full pagewidth
MGK622
release
receive
buffer
command
64-byte
FIFO
incoming
messages
message 3
message 2
message 1
25
24
23
22
21
20
19
18
17
16
28
27
26
receive
buffer
window
CAN address
Message 1 is now available in the receive buffer.
6.4.14.1
Descriptor eld of the receive buffer
The bit layout of the receive buffer is represented in Tables 34 to 36 for SFF and Tables 37 to 41 for EFF. The given
configuration is chosen to be compatible with the transmit buffer layout (see Section 6.4.13.2).
Table 34 RX frame information (SFF); CAN address 16
Notes
1. Frame format.
2. Remote transmission request.
3. Data length code bit.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF(1)
RTR(2)
0
DLC.3(3)
DLC.2(3)
DLC.1(3)
DLC.0(3)
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