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參數(shù)資料
| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 20/68頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | 935230900112 |
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2000 Jan 04
27
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. The SJA1000 will enter sleep mode if the sleep mode bit is set to logic 1 (sleep); then there is no bus activity and no
interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a
wake-up interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to
allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.
The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after SM is set LOW
(wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a wake-up
interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive this
message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of SM is
not possible in reset mode. After clearing of reset mode, setting of SM is possible first, when bus-free is detected
again.
2. A write access to the bits MOD.1 to MOD.3 is only possible, if the reset mode is entered previously.
3. This mode of operation forces the CAN controller to be error passive. Message transmission is not possible.
The listen only mode can be used e.g. for software driven bit rate detection and ‘hot plugging’. All other functions can
be used like in normal mode.
4. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset mode bit is also set to logic 1
(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next
positive edge of the internal clock which operates at half of the external oscillator frequency. During an external reset
the microcontroller cannot set the reset mode bit to logic 0 (absent). Therefore, after having set the reset mode bit to
logic 1, the microcontroller must check this bit to ensure that the external reset pin is not being held HIGH. Changes
of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit reflects the
synchronized status. After the reset mode bit is set to logic 0 the CAN controller will wait for:
a) One occurrence of bus-free signal (11 recessive bits), if the preceding reset has been caused by a hardware reset
or a CPU-initiated reset.
b) 128 occurrences of bus-free, if the preceding reset has been caused by a CAN controller initiated bus-off, before
re-entering the bus-on mode.
MOD.1
LOM
Listen Only Mode;
notes 2 and 3
1
listen only; in this mode the CAN controller would
give no acknowledge to the CAN-bus, even if a
message is received successfully; the error
counters are stopped at the current value
0
normal
MOD.0
RM
Reset Mode; note 4
1
reset; detection of a set reset mode bit results in
aborting the current transmission/reception of a
message and entering the reset mode
0
normal; on the ‘1-to-0’ transition of the reset mode
bit, the CAN controller returns to the operating
mode
BIT
SYMBOL
NAME
VALUE
FUNCTION
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| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
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