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參數(shù)資料
| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | 935230900112 |
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2000 Jan 04
37
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Table 21 Bit interpretation of bits ECC.4 to ECC.0; note 1
Note
1. Bit settings reflect the current frame segment to distinguish between different error events.
BIT ECC.4 BIT ECC.3 BIT ECC.2 BIT ECC.1 BIT ECC.0
FUNCTION
00011
start of frame
00010
ID.28 to ID.21
00110
ID.20 to ID.18
00100
bit SRTR
00101
bit IDE
00111
ID.17 to ID.13
01111
ID.12 to ID.5
01110
ID.4 to ID.0
01100
bit RTR
01101
reserved bit 1
01001
reserved bit 0
01011
data length code
01010
data eld
01000
CRC sequence
11000
CRC delimiter
11001
acknowledge slot
11011
acknowledge delimiter
11010
end of frame
10010
intermission
10001
active error ag
10110
passive error ag
10011
tolerate dominant bits
10111
error delimiter
11100
overload ag
If a bus error occurs, the corresponding bus error interrupt
is always forced, if enabled. At the same time, the current
position of the bit stream processor is captured into the
error code capture register. The content within this register
is fixed until the users software has read out its content
once. The capture mechanism is then activated again.
The corresponding interrupt flag located in the interrupt
register is cleared during the read access to the interrupt
register. A new bus error interrupt is not possible until the
capture register is read out once.
6.4.10
ERROR WARNING LIMIT REGISTER (EWLR)
The error warning limit can be defined within this register.
The default value (after hardware reset) is 96. In reset
mode this register appears to the CPU as a read/write
memory. In operating mode it is read only.
Note, that a content change of the EWLR is only possible,
if the reset mode was entered previously. An error status
change (see status register; Table 14) and an error
warning interrupt forced by the new register content will not
occur until the reset mode is cancelled again.
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