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| 型號： | 935225410112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 7/67頁 |
| 文件大?。?/td> | 400K |
| 代理商： | 935225410112 |
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1998 Apr 07
15
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
8
MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbytes external
data memory (of which the lower 256 bytes reside in the
internal AUX-RAM), 512 bytes internal data memory
(consisting of 256 bytes standard RAM and 256 bytes
AUX-RAM) and the 64 kbytes internal and external
program memory.
8.1
Program memory
The program memory address space of the P89C738
comprises an internal and an external memory portion.
The P89C738 has 64 kbytes of program memory on-chip.
The program memory can also be externally addressed up
to 64 kbytes. If the EA pin is held HIGH, the P89C738
executes out of the internal program memory. If EA pin is
held LOW, the P89C738 fetches all instructions from the
external program memory. Figure 8 illustrates the program
memory address space.
The security bit is always set in the P89C738 and
P89C739 to protect the ROM code. Table 2 lists the
access to the internal and external program memory by the
MOVC instructions when the security bit has been set to a
logic 1. If the security bit has been set to a logic 0 there are
no restrictions for the MOVC instructions.
Table 2
Internal and external program memory access
MOVC
INSTRUCTION
PROGRAM MEMORY ACCESS
INTERNAL
EXTERNAL
MOVC in internal
program memory
YES
MOVC in external
program memory
NO
YES
Fig.8 Program memory address space.
handbook, halfpage
MGK190
EXTERNAL
(EA = 0)
INTERNAL
(EA = 1)
PROGRAM MEMORY
65535
0
8.2
Internal data memory
The internal data memory is divided into three physically
separated parts: 256 bytes of RAM, 256 bytes of
AUX-RAM, and a 128 bytes Special Function Registers
(SFRs) area. These parts can be addressed as follows
(see Fig.9 and Table 3):
RAM locations 0 to 127 can be addressed directly and
indirectly as in the 80C51. Address pointers are R0 and
R1 of the selected register bank.
RAM locations 128 to 255 can only be addressed
indirectly. Address pointers are R0 and R1 of the
selected register bank.
AUX-RAM locations 0 to 255 are indirectly addressable
as the external data memory locations 0 to 255 with the
MOVX instructions. Address pointers are R0 and R1 of
the selected register bank and DPTR. When executing
from internal program memory, an access to AUX-RAM
0 to 255 will not affect the ports Port 0, Port 2,
P3.6 and P3.7.
The SFRs can only be addressed directly in the address
range from 128 to 255.
An access to external data memory locations higher than
255 will be performed with the MOVX DPTR instructions in
the same way as in the 80C51 structure, i.e. with Port 0
and Port 2 as data/address bus and P3.6 and P3.7 as write
and read timing signals. Note that the external data
memory cannot be accessed with R0 and R1 as address
pointer.
Figure 9 shows the internal and external data memory
address space. Chapter 17 shows the Special Function
Registers overview. Four 8-bit register banks occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations.
The stack can be located anywhere in the internal
256-byte RAM. The stack depth is only limited by the
available internal RAM space of 256 bytes. All registers
except the Program Counter and the four 8-bit register
banks reside in the SFR address space.
Table 3
Internal data memory access
MEMORY
LOCATION
ADDRESS MODE
RAM
0 to 127
direct and indirect
128 to 255
indirect only
SFR
128 to 255
direct only
AUX-RAM
0 to 255
indirect only with MOVX
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