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參數(shù)資料
| 型號： | 935225410112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 3/67頁 |
| 文件大?。?/td> | 400K |
| 代理商： | 935225410112 |
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1998
Apr
07
11
Philips
Semiconductors
Product
specication
8-bit
Flash
microcontrollers
P89C738;
P89C739
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6.2
Pin
description
Table 1
Pin description for DIP40; QFP44; PLC44; QFP64 and PLCC68.
SYMBOL
PIN(1)
DESCRIPTION
PLCC68
QFP64
PLCC44
QFP44
DIP40
P1.0/T2
19
11
16
2
1
Port 1: P1.0 to P1.7; 8-bit quasi-bidirectional I/O port. Port 1 can
sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs
without external pull-ups.
Port 1 alternative functions are: T2; Timer/event counter 2 external
event counter input (falling edge triggered). T2EX; Timer/event
counter 2 capture/reload trigger or external interrupt 2 input (falling
edge triggered).
P1.1/T2EX
21
13
15
3
2
P1.2
22
14
4
3
P1.3
23
15
13
5
4
P1.4
25
17
12
6
5
P1.5
27
19
1
7
6
P1.6
28
20
2
8
7
P1.7
29
21
3
9
8
RST
30
22
4
10
9
Reset; a HIGH level on this pin for two machine cycles while the
oscillator is running, resets the device. An internal pull-down resistor
permits power-on reset using only a capacitor connected to VDD.
After a Watchdog Timer overow this pin is pulled HIGH while the
internal reset signal is active.
P3.0/RXD/data
34
26
5
11
10
Port 3: P3.0 to P3.7; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 3 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
Port 3 alternative functions are: RXD/data; Serial Port data input
(asynchronous) or data input/output (synchronous).
TXD/clock; Serial Port data output (asynchronous) or clock output
(synchronous). INT0; External interrupt 0 or gate control input for
Timer/event counter 0. INT1; External interrupt 1 or gate control
input for Timer/event counter 1. T0; external input for Timer/event
counter 0. T1; external input for Timer/event counter 1.
WR; external data memory write strobe. RD; external data memory
read strobe.
P3.1/TXD/clock 39
29
7
13
11
P3.2/INT0
40
30
8
14
12
P3.3/INT1
41
31
9
15
13
P3.4/T0
42
32
10
16
14
P3.5/T1
43
33
11
17
15
P3.6WR
45
35
44
18
16
P3.7/RD
47
37
43
19
17
XTAL2
48
38
42
20
18
Crystal input 2: output of the inverting amplier that forms the
oscillator. This pin left open-circuit when an external oscillator clock
is used (see Figs 18 and 20).
XTAL1
49
39
41
21
19
Crystal input 1: input to the inverting amplier that forms the
oscillator, and input to the internal clock generator. Receives the
external oscillator clock signal when an external oscillator is used
(see Figs 18 and 20).
VSS
51
41
40
22
20
Ground: circuit ground potential.
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