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參數(shù)資料
| 型號： | 935212530518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 34/39頁 |
| 文件大?。?/td> | 289K |
| 代理商： | 935212530518 |
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1996 Jul 03
4
Philips Semiconductors
Preliminary specication
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
VSSD1
1
digital ground 1
DP4 to DP7
2 to 5
I/O
Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
RCV1
6
I/O
Raster control 1 for video port; depending on the synchronization mode, this
pin receives or provides a VS/FS/FSEQ signal.
RCV2
7
I/O
Raster control 2 for video port; depending on the synchronization mode, this
pin receives or provides an HS/HREF/CBL signal.
VSSD2
8
digital ground 2
VP0 to VP7
9 to 16
I
Video port; this is an input for CCIR 656 compatible multiplexed video data. If
the 16-bit DIG-TV2 format is used, then Y data is input.
VDDD1
17
I
digital supply voltage 1
SEL_ED
18
I
select encoder data; selects input data either from the MPEG port or from
the video port
VSSD3
19
digital ground 3
MP7 to MP0
20 to 27
I
MPEG port; it is an input for CCIR 656 style multiplexed YUV data.
VSSD4
28
digital ground 4
RCM1
29
O
Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal.
RCM2
30
O
Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG
decoder.
KEY
31
I
key signal for OVL (active HIGH)
OVL0 to OVL2
32 to 34
I
on-screen display data; this is the index for the internal OVL look-up tables
VSSD5
35
digital ground 5
CDIR
36
I
Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal,
if not LLC and CREF are generated by the internal crystal oscillator.
VDDD2
37
I
digital supply voltage 2
LLC
38
I/O
Line-locked clock; this is the 27 MHz master clock for the encoder. The
direction is set by the CDIR pin.
CREF
39
I/O
Clock reference signal; this is the clock qualier for DIG-TV2 compatible
signals. The polarity is programmable by software.
XTALO
40
O
crystal oscillator output (to crystal)
XTALI
41
I
Crystal oscillator input (from crystal). If the oscillator is not used, this pin
should be connected to ground.
VSSD6
42
digital ground 6
RTCI
43
I
Real time control Input; if the clock is provided by the SAA7151B or
SAA7111, RTCI should be connected to the RTCO pin of the decoder to
improve the signal quality.
AP
44
test pin (should be connected to digital ground for normal operation)
SP
45
test pin (should be connected to digital ground for normal operation)
VrefL
46
I
lower reference voltage input for the DACs
VrefH
47
I
upper reference voltage input for the DACs
VDDA1
48
I
analog positive supply voltage 1 for the DACs and output ampliers
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