參數(shù)資料
型號: 935212530518
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL ENCODER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 13/39頁
文件大小: 289K
代理商: 935212530518
1996 Jul 03
20
Philips Semiconductors
Preliminary specication
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 24 Logic levels and function of CCEN
Table 25 Logic levels and function of SRCM
Table 26 Subaddress 6E to 6F
Table 27 Subaddress 70
Note
1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events.
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
line 21 encoding OFF
0
1
enables encoding in eld 1 (odd)
1
0
enables encoding in eld 2 (even)
1
enables encoding in both elds
DATA BYTE
AS OUTPUT
FUNCTION
SRCM1
SRCM0
0
VS
vertical sync each eld
0
1
FS
frame sync (odd/even)
1
0
FSEQ
eld sequence, vertical sync every fourth eld (FISE = 1) or eighth
eld (FISE = 0)
1
not applicable
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 037H
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG=0to31 (1FH)
SBLBN
0
vertical blanking is dened by programming of FAL and LAL
1
vertical blanking is forced in accordance with CCIR-624 (50 Hz) or RS170A (60 Hz);
note 1
PHRES
selects the phase reset mode of the colour subcarrier generator; see Table 28
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