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參數(shù)資料
| 型號： | 935212530518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 15/39頁 |
| 文件大?。?/td> | 289K |
| 代理商： | 935212530518 |
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1996 Jul 03
22
Philips Semiconductors
Preliminary specication
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Table 31 Subaddress 7A
Table 32 Subaddress 7B to 7D
Slave Transmitter
Table 33 Slave Transmitter (slave address 89H or 8DH)
Table 34 No subaddress
DATA BYTE
DESCRIPTION
FLC1
FLC0
0
eld length control interlaced 312.5 lines/elds at 50 Hz, 262.5 lines/elds at 60 Hz
(reset default)
0
1
eld length control non-interlaced 312 lines/elds at 50 Hz, 262 lines/elds at 60 Hz
1
0
eld length control non-interlaced 313 lines/elds at 50 Hz, 262 lines/elds at 60 Hz
1
eld length control non-interlaced 313 lines/elds at 50 Hz, 262 lines/elds at 60 Hz
DATA BYTE
DESCRIPTION
FAL
rst active line = FAL + 4 for M systems; = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the rst eld synchronization pulse
LAL
last active line = LAL + 3 for M systems; = LAL for other systems, measured in lines
LAL = 0 coincides with the rst eld synchronization pulse
REGISTER
FUNCTION
SUBADDRESS
DATA BYTE
D7
D6
D5
D4
D3
D2
D1
D0
Status byte
VER2
VER1
VER0
CCRDO CCRDE
FSQ2
FSQ1
FSQ0
DATA BYTE
DESCRIPTION
VER
Version identication of the device. It will be changed with all versions of the IC that have different
programming models. Current version is 100 binary.
CCRDO
1 = closed caption bytes of the odd eld have been encoded.
0 = the bit is reset after information has been written to the subaddresses 67 and 68. It is set
immediately after the data have been encoded.
CCRDE
1 = closed caption bytes of the even eld have been encoded.
0 = the bit is reset after information has been written to the subaddresses 69 and 6A. It is set
immediately after the data have been encoded.
FSQ
State of the internal eld sequence counter.
Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH.
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