參數(shù)資料
型號： 935211970557
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-393, QFP-64
文件頁數(shù)： 65/67頁
文件大小： 443K
代理商： 935211970557
1998 May 15
7
Philips Semiconductors
Product specication
Video Input Processor (VIP)
SAA7111
RES
32
23
O
Reset output (active LOW); sets the device into a dened state.
All data outputs are in high impedance state. The I2C-bus is reset
(waiting for start condition) note 4.
CE
33
24
I
Chip enable; connection to ground forces a reset.
VDD4
34
25
P
Positive digital supply voltage 4 (+5 V).
VSS4
35
26
GND
Digital ground for positive supply voltage 4.
n.c.
36
Not connected.
n.c.
37
Not connected.
HS
38
27
O
Horizontal sync output signal (programmable); the positions of the
positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64
s) via I2C-bus bytes HSB and HSS.
Fine position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.
RTS1
39
28
O
Two functions output; controlled by I2C-bit RTSE1.
RTSE1 = 0: PAL line identier (LOW = PAL line); indicates the
inverted and non-inverted R
Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.
RTS0
40
29
O
Two functions output; controlled by I2C-bit RTSE0.
RTSE0 = 0: odd/even eld identication (HIGH = odd eld).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.
VS
41
30
O
Vertical sync output signal (enabled via I2C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deection controller.
HREF
42
31
O
Horizontal reference output signal (enabled via I2C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.
VSS3
43
32
GND
Digital ground for positive supply voltage 3.
VDD3
44
33
P
Positive digital supply voltage 3 (+5 V).
VPO (15 to 10)
45 to 50
34 to 39
O
Digital VPO-bus (Video Port Out) output signal; higher bits of the
16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I2C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.
VSS2
51
40
GND
Digital ground for positive supply voltage 2.
VDD2
52
41
P
Positive digital supply voltage 2 (+5 V).
SYMBOL
PINS
I/O
DESCRIPTION
PLCC68
QFP64
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