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參數(shù)資料
| 型號(hào)： | 935200940112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP52 |
| 封裝： | PLASTIC, SOT-247, SDIP-52 |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 236K |
| 代理商： | 935200940112 |
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March 1994
17
Philips Semiconductors
Objective specication
Integrated PAL and PAL/NTSC TV
processors
TDA8360; TDA8361; TDA8362
Delay line and peaking circuit
Y DELAY LINE
td
delay time
note 7
480
ns
B
bandwidth of internal delay line
note 7
8
MHz
PEAKING CONTROL
; NOTE 28, SEE ALSO FIG.6 (PIN 14)
tW
width of preshoot or overshoot
at 50% of pulse;
note 7
160
ns
Scth
peaking signal compression
threshold
50
IRE
I14
input current when no video input
signal present
1
mA
VI
voltage level to switch off peaking
7
V
Horizontal and vertical synchronization circuits
SYNC VIDEO INPUT (TDA8361, TDA8362; PINS 13 AND 15)
V13
sync pulse amplitude
referenced to pin 15;
note 3
50
300
mV
SL
slicing level
note 29
50
%
VERTICAL SYNC
tW
width of the vertical sync pulse
without sync instability
note 30
22
s
HORIZONTAL OSCILLATOR
ffr
free running frequency
note 44
15625
Hz
f
fr
spread on free running frequency
±2%
f
osc/VP
frequency variation with respect to
the supply voltage
VP = 8 V ±10%;
note 7
0.2
0.5
%
f
osc/T
frequency variation with temperature
Tamb = 25 °C ±50 °C;
note 7
1
Hz/K
f
osc( max)
maximum frequency deviation at the
start of the horizontal output
75
%
FIRST CONTROL LOOP; NOTE 31 (FILTER CONNECTED TO PIN 40)
fHR
holding range PLL
±0.9
±1.2
kHz
fCR
catching range PLL
note 7
±0.6
±0.9
kHz
S/N
signal-to-noise ratio of the video input
signal at which the time constant is
switched
20
dB
HYS
hysteresis at the switching point
3
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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