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參數(shù)資料
| 型號： | 935185240518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SOT-266, SSOP-20 |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 251K |
| 代理商： | 935185240518 |
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1997 Feb 27
8
Philips Semiconductors
Product specication
Power amplier controller for GSM and
PCN systems
PCF5075
6.4
Ramp generation (see Fig.3)
The circuit is activated with the PD signal going LOW
before time mask ‘AS’ and deactivated after
ramping-down, by PD going HIGH between ‘GS’ and ‘HS’.
For the (usual) ‘power-down burst mode’ application in
GSM/PCN mobile stations, the RF input power at the
power module must be activated between ‘AS’ and ‘BS’
(when the home position at VO(INT) has already reached its
stable value) and deactivated between ‘GS’ and ‘HS’. This
is necessary for many types of power modules to meet the
70 dB margin. For quick restart after ramping-down see
Chapter 12.
A ramp-up is started by a positive edge on TRIG. To be
able to detect a quick restart (base station applications
only) the TRIG signal is internally delayed by two clock
periods. Because of this, all other internal signals are
delayed by two clock periods with respect to the signal at
pin TRIG.
Figure 3 shows a possible relationship between the chip
timing (points ‘B’, ‘C’, ‘E’ and ‘G’) and the GSM-mask
standard (points ‘AS’, ‘BS’, ‘CS’, ‘DS’, ‘ES’, ‘FS’, ‘GS’ and
‘HS’). However, the user is free to choose t1 and t2
independently so that the mask is not violated.
6.4.1
DESCRIPTION OF SIGNALS
Signals starting at a stable home position of VO(INT) at time
B
2Tcy are considered.
The integrator output voltage is regulated to the value
defined in the VHOME register. The output of the slope
generator is VSR 2VD1 +VKICK and is connected to the
positive input VINT(p) of operational amplifier OP4 (VKICK is
defined by the ‘Vk’-bits in the VKICK register). Two clock
periods after a positive edge on TRIG the integrator start
condition circuitry is turned off and OP4 is switched into an
integrator configuration (‘B’). Now the HPA switches are
open. Due to the positive differential input voltage VKICK,
the integrator output will start to rise. After 18Tcy (‘C’) the
output of DAC8 is connected to the adder and slope
generator block. The input of the 8-bit DAC comes from
generator will generate a smooth curve between the
former and the new output value of the adder block.
The voltage VRAMPR at the end is VSR 2VD1 + VPL, thus
the power amplifier is ramped-up via the integrator in
approximately 22Tcy.
This condition is stable providing TRIG remains HIGH.
Two clock periods after a negative edge at TRIG the
ramp-down is started (‘E’).The adder output voltage will
change to VSR 2Vd1 VQRS (VQRS = 100 mV typ.),
because DACA becomes inactive and QRSA active.
This additional subtraction of 100 mV causes a
ramp-down with a shortened tail.The slope generator
again generates a smooth curve between the new adder
output voltage and the old adder output voltage. The slope
generator must have reached its final value 38Tcy after the
recognized falling edge of TRIG because the signal HPA
is activated again and by that turning the integrator into its
‘home position’ (‘G’).The integrator output voltage will be
regulated once more to the value defined in the VHOME
register. The adder output voltage is VSR 2VD1 +VKICK.
The voltage VKICK is subtracted at VINT(n) by VKOMP while
the home position is active (see Fig.1). Thus the resulting
voltage at VO(INT) has the programmed value VHOME.
Figures 4, 5 and 6 show measurements of the circuit in
application.
6.4.2
STABILITY
Figure 6 shows the result of a special test. A static power
level was chosen where the steepness of the control curve
of a worst case power module sample has the highest
value. This value usually is approximately 6 to 10 dB less
than the maximum possible power. Capacitors C1 and C2
are now reduced to the point where the loop is close to the
limit of stability. A gain peaking at the critical frequency
occurs and noise increases. By this easy procedure the
critical frequency and the critical value for C1 = C2 can be
found. These capacitances must now be increased by a
factor of 2 to 4 for sufficient stability reserve.
6.4.3
CLOCK INFLUENCE
The resulting loop band width must be smaller than the
internal clock frequency fclk = 2.166 MHz. A gain peaking
effect at fclk must be avoided, low pass filters between
pin VO(INT) and the input of the power module will reduce
the stability margin and this can cause an unwanted gain
at fclk. As shown in the block diagram (see Fig.1) a
non-critical serial resonant circuit at pin VINT(p) is
recommended.
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