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參數(shù)資料
| 型號： | 935185240518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SOT-266, SSOP-20 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 251K |
| 代理商： | 935185240518 |
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1997 Feb 27
7
Philips Semiconductors
Product specication
Power amplier controller for GSM and
PCN systems
PCF5075
If the chip is used in the burst mode it is important to switch
on the PCF5075 before the power module or the
RF-power; otherwise it is possible that a positive spike at
V(INT)o will open the power module. A minimum period of
tON = 400 s should be allowed between activating the
PCF5075 (via PD) and activating the power module
(externally, generally via TRIG). See Fig.3.
6.2.2
POWER-DOWN (PD) LOW
The whole chip is active. Pin CL13 clocks the internal state
machine as well as the adder and slope generator. Every
change at TRIG is recognized if the master clock is
running. The contents of the serial bus registers are
processed. If the master clock is switched off during
power-up, the state machine is stopped and the output of
the adder/slope generator becomes undefined.
Nevertheless, by reactivating the master clock, the output
of the adder/slope generator will settle to the old values
again.
6.3
The analog integrating controller
The analog integrating controller consists of three
operational amplifiers (OP1, OP2 and OP4) and one
comparator. OP1 and OP2 are only used for buffering
purposes, OP4 is used to form a differential integrator.
The comparator is used to limit the integrator output
voltage to the value selected by the ‘lim’-bits in the serial
register.
A two (Schottky) diode external rectifier is connected to
pins VSR, VS2, IBIAS and VS1.
The SC-Adder block basically generates the voltage
VSR 2VD1 +VPL.The differential integrator then
integrates the difference of this voltage and the voltage
VSR 2VD1 +VRFIN. The integrator output voltage VO(INT)
is used to control the power amplifier module.
Table 1
Denition of some voltages (see Fig.1)
SYMBOL
DESCRIPTION
VSR
bias voltage output for sensor (band gap voltage), typically 1.25 V
VD1
voltage over the (external) Schottky diode D1
VPL
voltage determining the power level; it is generated in the SC-Adder block if switch DACA is closed
(i.e. if the signal DACA is HIGH); equals 2.4 times the DAC8 output
VRFIN
voltage difference at pin VS1 when RF is rectified at the sensor diode D2
VBVS1
buffered voltage from pin VS1
VKICK
kick voltage; if KICKA is HIGH, DAC8 outputs this voltage
VKOMP
voltage at R3 if the circuit is switched to the home position by HPA; VKOMP compensates VKICK at R2
VRAMPR
buffered output voltage of the slope generator; steady state limits of some succeeding ltered voltage
steps (not 1:1 visible at pin VINT(p))
HPA/KICKA active: VSR 2VD1 +VKICK
DACA active: VSR 2VD1 +VPL
QRSA active: VSR 2VD1 VQRS
VHOMEIN
if HPA is active, DAC6 outputs the value of the VHOME register which is directly visible only at pin 18;
VHOMEIN also contains the diode forward voltages nVF (with n = 0,1 or 2; VF ≈ 700 mV at Tamb =27 oC)
VQRS
0 or 100 mV; 0 V only if a ‘Quick Restart’ condition is detected; otherwise, if QRSA is active, DAC8
outputs 100 mV; this voltage is inverted by the adder and causes a ramp-down with a shortened tail
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