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參數(shù)資料
| 型號： | 935185240518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SOT-266, SSOP-20 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 251K |
| 代理商： | 935185240518 |
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1997 Feb 27
6
Philips Semiconductors
Product specication
Power amplier controller for GSM and
PCN systems
PCF5075
6
FUNCTIONAL DESCRIPTION
6.1
General
This CMOS device integrates operational amplifiers, two
digital-to-analog converters and a serial interface to
implement an ‘Integrating-Controller’. It is designed to
control both the power level and the up and down-ramping
of GSM-transmit bursts.
The GSM/PCN power-up power-down ramping curves are
generated on-chip, using an internal clock frequency of
2.166 MHz (Tcy = 1/fclk), that is generated internally by
dividing the external 13 MHz clock by six.
Generally, the power amplifier is ramped-up after a rising
edge on TRIG (pin 10) and ramped-down after a falling
edge. When TRIG goes LOW for less than two clock
periods (2Tcy), a special function for base station
applications is activated (see Chapter 12).
When DTX (pin 9) becomes active during a ramp-up,
ramping is stopped and a normal ramp-down is executed
thereby turning the power module off. To restart the ramp
generator, DTX and TRIG have to go LOW (TRIG has to
stay LOW for more than two clock periods). The next
LOW-to-HIGH transition will cause a ramp-up again.
The contents of the power-level register (PL7-to-PL0)
determines which of 256 possible values the top of the
clock period burst will have.
To match the controller to different power modules and
sensors, several parameters must be adjusted:
1. The typical value of the external capacitors
C1 and C2. C1 determines the maximum bandwidth
of the power control loop, depending on the highest
steepness of the control curve of the power module
and on the sensor attenuation (see Fig.4).
2. The upper voltage limit of VO(INT) (pin 18). To protect
the power module; the output of VO(INT) can be limited
to 3.75 V, 3.1 V or 2.35 V, depending on the contents
of the limiter register (lim1-to-lim0). The fourth limiter
register word can be used to switch the limiter option
off. This limiting results in a ringing at VO(INT)
(200 mV (p-p) typ.) but, because the power module is
in saturation, it will not transfer the ringing to the
antenna.
3. The HOME VO(INT) position. The integrator output
voltage at home position (PD and TRIG LOW) must be
programmed with the VHOME register. Bits Vh5-to-Vh0
are fed into a 6-bit DAC that generates a part of
VHOME.
4. The temperature behaviour of the home position.
Bits Dvh1 and Dvh0 must be used to add 0, 1 or 2
internally generated diode voltages to VHOME. In this
manner it is possible to compensate for a possible
temperature dependence (
2 mV/°C or 4 mV/°C) of
the control curves of the power module.
5. The KICK voltage. The 6 bits of the KICK voltage
register (Vk5-to-Vk0) determine the differential
integrator input voltage just after a ramp-up starting
signal is detected.
The register information is written via a three-wire serial
bus (see Sections 6.5 and 6.6).
The DF output (pin 12) is a general purpose pin which can
have three different states, LOW, HIGH and 3-state,
depending on the values of DF0 and DF1 in the serial
register.
Separate power supply pins are provided for the analog
and digital blocks.
6.2
Primary start condition
When the power supply is first switched on, the PCF5075
is in an undefined state because the chip has neither a
power-on-reset nor a reset pin. Initialisation of the digital
part is therefore necessary.
The easiest way of doing this is to perform a short dummy
ramp-up/ramp-down sequence, apply the 13 MHz master
clock, make PD LOW and then toggle TRIG
LOW-HIGH-LOW for more than two clock periods in the
HIGH state. The chip will stay initialized as long as the
supplies are on. After this, recognition of the 13 MHz
master clock and TRIG will be influenced by PD.
6.2.1
POWER-DOWN (PD) HIGH
The serial bus interface is operating, and all registers can
be programmed, but no effect will be seen on any pin.
The contents of the registers are passed to the rest of the
circuit only during power-up and with the 13 MHz master
clock applied.
Also, because the LOW-input swing buffer at pin CL13 is
switched off, neither the adder nor the slope generator will
function. This means that after the chip is powered-up, the
outputs have to settle again to the programmed register
values. The settling time is dominated by the slow
power-up of the band gap of typically 250
s.
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