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參數(shù)資料
| 型號： | 933728090112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 136K |
| 代理商： | 933728090112 |
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2003 Jan 27
5
Philips Semiconductors
Product specication
Clock/calendar with serial I/O
PCF8573
7
FUNCTIONAL DESCRIPTION
7.1
Oscillator
The PCF8573 has an integrated crystal-controlled
oscillator which provides the timebase for the prescaler.
The frequency is determined by a single 32.768 kHz
crystal connected between OSCI and OSCO. A trimmer is
connected between OSCI and VDD.
7.2
Prescaler and time counter
The prescaler provides a 128 Hz signal at the FSET output
for fine adjustment of the crystal oscillator without loading
it. The prescaler also generates a pulse once a second to
advance the seconds counter. The carry of the prescaler
and the seconds counter are available at the outputs SEC,
MIN respectively, and are also readable via the I2C-bus.
The mark-to-space ratio of both signals is 1 : 1. The time
counter is advanced one count by the falling edge of output
signal MIN. A transition from HIGH-to-LOW of output
signal SEC triggers MIN to change state.
The time counter counts minutes, hours, days and months,
and provides a full calendar function which needs to be
corrected only once every four years - to allow for
leap-year. Cycle lengths are shown in Table 1.
7.3
Alarm register
The alarm register is a 24-bit memory. It stores the
time-point for the next setting of the status flag COMP.
Details of writing and reading of the alarm register are
included in the description of the characteristics of the
I2C-bus.
7.4
Comparator
The comparator compares the contents of the alarm
register and the time counter, each with a length of 24 bits.
When these contents are equal the flag COMP will be set
4 ms after the falling edge of MIN. This set condition
occurs once at the beginning of each minute. This
information is latched, but can be cleared by an instruction
via the I2C-bus. A clear instruction may be transmitted
immediately after the flag is set and will be executed. Flag
COMP information is also available at the output COMP.
The comparison may be based upon hours and minutes
only if the internal flag NODA (no date) is set. Flag NODA
can be set and cleared by separate instructions via the
I2C-bus, but it is undefined until the first set or clear
instruction has been received. Both COMP and NODA
flags are readable via the I2C-bus.
handbook, halfpage
PCF8573T
MBL806
1
2
3
4
5
6
7
8
A0
A1
COMP
SDA
SCL
EXTPF
PFIN
VSS2
VDD
VSS1
OSCO
OSCI
TEST
FSET
SEC
MIN
16
15
14
13
12
11
10
9
Fig.3 Pinning diagram (SO16).
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