參數(shù)資料
型號(hào)： 9250BF-27LFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56
文件頁(yè)數(shù)： 15/17頁(yè)
文件大?。?/td> 221K
代理商： 9250BF-27LFT
7
ICS9250-27
0395D—10/25/05
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
2
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
-100
CL = 0 pF; Select @ 66 MHz
97
115
CL = 0 pF; Select @ 100 MHz
91
110
CL = 0 pF; Select @ 133 MHz
100
165
CL = Max loads; Select @ 66 MHz
295
330
CL = Max loads; Select @ 100 MHz
280
320
CL = Max loads; Select @ 133 MHz
300
395
CL = 0 pF; Select @ 66 MHz
16
19
CL = 0 pF; Select @ 100 MHz
25
35
CL = 0 pF; Select @ 133 MHz
26
40
CL = Max loads; Select @ 66 MHz
19
30
CL = Max loads; Select @ 100 MHz
34
50
CL = Max loads; Select @ 133 MHz
40
70
IDD3.3PD
CL = Max loads
220
400
IDD.25PD
Input address VDD or GND
<1
10
Input Frequency
Fi
VDD = 3.3 V
12
14.318
16
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
5
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
5
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
5
ms
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
Delay
1
mA
Input Capacitance
1
IDD2.5OP
A
Powerdown Current
Operating Supply
Current
Input Low Current
A
mA
IDD3.3OP
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