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參數(shù)資料
| 型號： | 9248YF-95LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE ANNEALED, SSOP-48 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 294K |
| 代理商： | 9248YF-95LF |
9
ICS9248- 95
310D—04/12/05
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-95. It is used to turn off the PCICLK [4:0] clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-95 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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