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參數(shù)資料
| 型號： | 9248YF-95LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE ANNEALED, SSOP-48 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 294K |
| 代理商： | 9248YF-95LF |
6
ICS9248-95
310D—04/12/05
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
X
#
0
S
F
d
e
h
c
t
a
L
6
t
i
B7
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
I
C
P
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B3
11
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B2
11
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B1
11
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B0
11
)
t
c
a
n
I
/
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c
A
(
1
K
L
C
I
C
P
0
t
i
B8
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B6
41
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
5
t
i
B-
1
)
d
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v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
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B9
31
)
t
c
a
n
I
/
t
c
A
(
F
_
M
A
R
D
S
2
t
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B2
41
)
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n
I
/
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A
(
2
K
L
C
U
P
C
1
t
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B3
41
)
t
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n
I
/
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c
A
(
1
K
L
C
U
P
C
0
t
i
B5
41
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
U
P
C
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B7
11
)
e
v
i
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c
a
n
I
/
e
v
i
t
c
A
(
1
M
A
R
D
S
6
t
i
B8
11
)
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v
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c
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n
I
/
e
v
i
t
c
A
(
0
1
M
A
R
D
S
5
t
i
B0
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
9
M
A
R
D
S
4
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B1
21
)
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v
i
t
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n
I
/
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v
i
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c
A
(
8
M
A
R
D
S
3
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B8
21
)
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v
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v
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A
(
7
M
A
R
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2
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B9
21
)
e
v
i
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n
I
/
e
v
i
t
c
A
(
6
M
A
R
D
S
1
t
i
B1
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
M
A
R
D
S
0
t
i
B2
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
M
A
R
D
S
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