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參數(shù)資料
| 型號： | 9248YF-20LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | 9248YF-20LF |
6
ICS9248-20
0276E—12/15/08
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-20 prior to its control
action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down
state.When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal
oscillator.The power on latency is guaranteed to be less than 3ms.The power down latency is less than three CPUCLK
cycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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